In certain Arm CPUs, a CPP RCTX instruction executed on one Processing Element (PE) may inhibit TLB invalidation when a TLBI is issued to the PE, either by the same PE or another PE in the shareability domain. In this case, the PE may retain stale TLB entries which should have been invalidated by the TLBI.
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No Fix Known
No patch has been released yet. Apply workarounds or mitigations where available.
| Vendor | Product | Versions | Fixed In |
|---|---|---|---|
| arm | c1-ultra_firmware | - | - |
| arm | c1-premium_firmware | - | - |
| arm | cortex-a710_firmware | - |
Published
CVE disclosed publicly
Last Modified
Most recent update
Indexed to CVEInsight
Added to this platform
AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
11
Affected Products
2
References
arm / c1-ultra_firmware
| - |
| arm | cortex-x2_firmware | - | - |
| arm | cortex-x3_firmware | - | - |
| arm | cortex-x4_firmware | - | - |
| arm | cortex-x925_firmware | - | - |
| arm | neoverse-v2_firmware | - | - |
| arm | neoverse-v3_firmware | - | - |
| arm | neoverse-v3ae_firmware | - | - |
| arm | neoverse-n2_firmware | - | - |
CVSS:3.1/AV:L/AC:L/PR:H/UI:N/S:C/C:H/I:H/A:N
Exploitability
Impact